1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, a semiconductor device, a solid-state imaging device, and a solid-state imaging apparatus. Specifically, the present invention relates to a method of manufacturing a semiconductor device and a semiconductor device in which isolation of a transistor is performed with a diffusion layer and to a solid-state imaging device and a solid-state imaging apparatus in which isolation of a transistor is performed with a diffusion layer.
2. Description of the Related Art
Generally, in MOS semiconductor devices, local oxidation of silicon (LOCOS) has long been used for isolation. However, in recent years, a shallow trench isolation (STI) method has been used for isolation in order to increase density.
It has become increasingly common to employ STI for isolation also in a solid-state imaging device such as a CMOS sensor.
FIG. 13 is a schematic view for illustrating the sectional structure of a main portion of a solid-state imaging device in which the STI method is used for isolation.
In a solid-state imaging device 101 shown herein, a p-type semiconductor well region 103 is formed on an n-type silicon substrate 102. A trench 104 is formed in the p-type semiconductor well region 103, and a silicon dioxide layer 105 is buried in the trench 104. With such a configuration, an isolation region, i.e., an STI region 106, is obtained for isolation within a pixel and between adjacent pixels.
The STI region 106 isolates adjacent pixels 110A and 110B, and isolates photodiodes PD, multiple transistors, and the like in the respective pixels 110A and 110B from one another.
It is noted that forming a lightly doped drain region in a source region or a drain region can improve transistor characteristic regarding noise or the like.
In the past, it has been generally considered that the transistor characteristic is not improved unless a lightly doped drain region is formed throughout all of the source region and the drain region. Thus, in order to reliably form a lightly doped drain throughout all of the source region and the drain region with consideration to a manufacturing error and the like, ion implantation has been performed using a mask including an opening portion 107 having a wider width than a gate electrode 130, as shown in FIGS. 14A and 14B. Therefore, a lightly doped drain region 108 has been formed also in the STI region 106 located on the outside of the gate electrode 130 in the width direction.
Note that a width of a gate electrode refers to the length of the gate electrode in the width direction of a current path of a transistor, and is the length shown by a reference symbol W in FIG. 14A. FIG. 14A shows a plan view of the transistor, and FIG. 14B shows a sectional view along line XIVB-XIVB in FIG. 14A. Further, in FIGS. 14A and 14B, reference numeral 109 denotes the source/drain region and reference numeral 110 denotes a resist that functions as a mask material.
The STI method described above is advantageous in that a fine isolation region is formed since the deep trench 104 is formed in the silicon substrate and the isolation region 106 is formed by burying the silicon dioxide layer 105.
However, due to the difference in coefficient of thermal expansion or the like between the deeply buried silicon dioxide layer 105 and the silicon substrate, there is a problem that a crystal defect due to thermal stress easily occurs.
Although efforts have been made by applying a taper shape or the like in STI, applying the taper shape narrows the area for the photodiode PD, leading to a decrease in saturation signal amount or sensitivity.
Also, in the STI method described above, a p+ region 100 is formed (see FIG. 13) at the boundary between the silicon dioxide layer 105 in the trench 104 and the photodiode PD in order to prevent dark current or a white defect. However, thermal diffusion causes the p+ region 100 to expand toward the photodiode PD side to narrow the area for the photodiode PD, leading to a decrease in saturation signal amount or sensitivity.
Thus, in order to increase the saturation signal amount by reducing the width of the isolation region and increasing the photodiode area, isolation using a diffusion layer implanted with an impurity has been performed (for example, see Japanese Unexamined Patent Application Publication No. 2007-158031).